All published memory-market news.

Marvell introduced technologies at FMS 2026 that address memory pressure in large AI inference deployments. The portfolio covers SSD-side infrastructure, CXL-based expansion at the rack level, and optical links for shared memory across larger systems. The focus is the growth of key-value cache requirements as models use longer context windows and produce more memory traffic. For the memory market, Marvell's announcement is less about selling DRAM or NAND directly and more about enabling architectures that can consume those resources more efficiently. If hyperscalers adopt more disaggregated designs, demand could shift toward higher-capacity SSDs, CXL memory modules, and networking components that keep accelerators supplied with data.

A Counterpoint Research update cited by TechPowerUp shows Samsung retaining the largest share of global DRAM revenue in the second quarter of 2026. Samsung is reported at 39%, while SK hynix holds about 26% after strong year-over-year revenue growth but a lower share than a year earlier. The same report says South Korean suppliers together account for 65% of global DRAM revenue. The data points to a market where higher prices for mainstream DRAM and HBM are lifting supplier revenue, while share shifts depend on product mix, execution, and contract strategy. SK hynix is described as leaning into longer customer agreements with preset pricing terms, while Micron is characterized as gaining ground. For buyers, the key signal is that pricing strength is broad enough to expand the revenue pool even when vendor rankings move.

Montage Technology is beginning trial production of a CXL 3.2 controller designed for memory expansion in AI infrastructure. The product targets systems that need to attach and share more memory without tying every capacity increase directly to a new processor or accelerator configuration. For the server market, this points to continued investment in CXL as a way to address memory capacity pressure created by larger AI workloads. The near-term price effect is limited because controller qualification does not immediately create new DRAM supply. Still, broader CXL adoption could change how data centers consume memory by making pooled capacity easier to deploy across servers.

Nanya said its board approved a multi-year investment program for Fab5A running from 2026 through 2029, with spending of up to NT$346.6 billion. The project spans 1b through 1e 10 nm-class DRAM nodes and introduces EUV lithography. The company also raised its 2026 capital expenditure budget to NT$69.7 billion, with the additional allocation aimed at equipment prepayments to keep the project on schedule. According to the roadmap described in the source, wafer output is expected to begin in the second half of 2027, rise to 30,000 wafers per month in 2028, and reach 35,900 wafers per month in 2029, with longer-term capacity planned at about 45,000 wafers per month. Nanya also said 1c pilot production has started and that 1d is moving toward pilot production. For the memory market, the announcement points to a larger long-range DRAM supply base rather than an immediate shift in available output. Near-term pricing remains supported by the recent strength in DRAM, especially DDR4, but the scale of this expansion indicates Nanya is positioning for more advanced process competition and higher future supply flexibility.

CoreWeave has arranged several years of priority enterprise SSD supply from Solidigm. The agreement is notable because AI cloud operators are starting to reserve storage capacity in advance, much as they already plan around accelerator availability. For NAND and enterprise SSD vendors, that points to steadier demand from AI infrastructure and less uncommitted capacity for high-capacity drives. It also moves flash procurement earlier in data-center planning, especially for large training and inference environments that need consistent storage throughput. If similar agreements spread across the cloud sector, enterprise SSD allocation could tighten and support NAND pricing.

SK hynix set a 54.3 trillion won investment plan across two Korean production projects aimed at future AI memory demand. The budget is divided between 35.2 trillion won for Yongin Y2 and 19.1 trillion won for Cheongju M17. Cleanroom openings are planned for June 2029 at Y2 and December 2028 at M17. The announcement is a long-horizon capacity signal rather than immediate market relief. It shows that SK hynix is preparing for sustained demand from AI servers across HBM, DRAM, and NAND, while also reminding buyers that advanced memory supply takes years to bring online. Capacity decisions being made now are more likely to shape late-decade pricing than the current cycle.

ChangXin Memory Technologies is evaluating another DRAM manufacturing site in China while pursuing a far larger role in global memory supply by 2030. If the current project pipeline is built out, CXMT's output could rise sharply over the next several years and give buyers a broader source of mainstream DRAM. The main constraint is execution. Limited access to advanced chipmaking equipment could slow the company's move into higher-end nodes and keep Samsung, SK hynix, and Micron ahead in premium segments. For pricing, this is not near-term supply relief because fabs take years to qualify and ramp. Over a longer horizon, a successful CXMT buildout would add competitive pressure in commodity DRAM, while tooling limits would keep that pressure uneven.

TSMC reportedly has a large inventory of Apple processors awaiting final packaging because the required DRAM has not arrived from Apple's memory suppliers. The issue centers on package-on-package integration, where LPDDR5X is placed with the application processor rather than installed elsewhere on the board. That makes memory availability a direct gating item for finished chip supply. The report highlights how tight mobile DRAM availability can ripple beyond memory buyers and affect semiconductor packaging schedules. Apple is said to rely mainly on Micron for LPDDR5X while also sourcing from SK hynix and Samsung. For the memory market, the signal is that leading smartphone demand is competing for constrained high-end DRAM at a sensitive point in the product cycle. That supports the broader view that mobile DRAM pricing power remains with suppliers until allocations loosen.

This is a stronger signal than earlier validation-only reports because it places CXMT closer to a manufacturing ramp. The reported LPDDR6 parts are 16Gb chips in package-on-package form, aimed at mobile memory use cases where Samsung, SK hynix, and Micron have historically held technology leadership. Risk production does not guarantee high-volume yield or major customer wins, but it suggests Chinese mobile DRAM competition is advancing faster than many buyers expected.

The pricing detail matters more than the product itself. If CXMT-based retail DDR5 appears near premium kit pricing, early supply may be constrained, positioned for margin, or carrying qualification and branding costs that prevent immediate discounting. That weakens the assumption that Chinese DRAM automatically creates near-term consumer price relief. Over time CXMT capacity could still pressure mainstream DRAM, but this listing suggests the first visible modules may not reset market pricing on their own.

This is a direct example of storage moving closer to the memory hierarchy. As inference context windows grow, HBM and DRAM alone can be too expensive or capacity-limited for every layer of cached data. ScaleFlux is positioning high-endurance SSDs as a shared tier that can sit below faster memory while still serving AI workloads. For RamTrend, the signal is that AI systems are creating new requirements for enterprise SSD endurance, telemetry, and placement controls, potentially supporting premium NAND demand even when the product is not a conventional SSD refresh.

The numbers are infrastructure-wide, not memory-specific, but the memory read-through is clear. AI data-center spending pulls on GPUs, custom accelerators, HBM, server DRAM, networking, and storage at the same time. If hyperscalers keep expanding capex, memory suppliers retain demand support for premium products even if commodity segments behave differently. The main caveat is that the article does not break out HBM or DRAM purchasing, so this should be treated as a demand backdrop rather than a direct price quote.

The benchmark itself is not a pricing report, but the premise is a useful consumer-memory signal. When system builders consider one DDR5 DIMM instead of two, it means memory cost has become noticeable enough to affect configuration choices. AMD 3D V-Cache systems may hide part of the performance penalty, but the tradeoff still shifts how entry and midrange gaming PCs are specified. RamTrend should treat this as evidence that DDR5 inflation is reaching end-system design decisions, not just component quotes.

The accelerator-volume claim is upstream of memory procurement, but it matters for HBM and advanced packaging demand. Large custom AI accelerator programs still need high-bandwidth memory and tightly integrated system designs, even when they do not use Nvidia GPUs. If Google scales TPUs aggressively, memory suppliers would see another demand pool tied to hyperscaler-owned silicon. The impact is uncertain because the report does not state memory configurations or supplier awards, but the direction is supportive for premium AI memory.

This is not a flash-memory pricing item, but it is relevant to the broader storage stack serving AI infrastructure. If nearline HDD supply remains allocated years ahead, cloud operators may have less flexibility across storage tiers, including SSD and NAND-heavy architectures used around training and inference pipelines. For RamTrend, the useful takeaway is that AI data growth is pressuring capacity planning beyond HBM and DRAM, extending into bulk storage where hyperscaler commitments can shape component procurement cycles.

This is an event-preview signal, not a price report. The useful point for RamTrend is that memory is being discussed as part of system-level AI integration alongside compute and optical interconnect. The planned Memory Executive Summit focus on HBM reflects how bandwidth and data movement remain gating factors for AI training and inference. That keeps advanced memory vendors exposed to AI platform design decisions, even when pricing is set elsewhere in the supply chain.

The main signal is strategic breadth. SK hynix is positioning tiered memory as AI models outgrow one memory class, with HBM for bandwidth, CXL for capacity expansion, HBF as a flash-based near-compute tier, and products such as SOCAMM2 and DDR5 RDIMM for server designs. This supports the view that AI memory demand is spreading across multiple form factors. It also reinforces that HBM leadership is only one part of the AI infrastructure memory stack.

The story highlights a split inside the memory upcycle. SK hynix remains strongly positioned in HBM, but that focus can limit how much it participates in conventional DRAM expansion. Samsung and Micron appear better placed to capture price improvement in traditional DRAM and NAND markets. For RamTrend, this supports tracking supplier mix separately: HBM leadership and commodity DRAM leverage are not the same exposure in the current cycle.

The report is an important competitive signal for mobile memory. LPDDR6 is a future-facing product class, so the immediate price effect is limited, but CXMT reaching late validation would show faster progress toward higher-value DRAM segments. Samsung, SK hynix, and Micron still have deep technology, qualification, and customer advantages, yet CXMT's progress could matter for non-U.S. device supply chains and for long-term pricing pressure in mobile DRAM.

HBF is positioned between DRAM or HBM and conventional SSD storage. The specification describes NAND stacks up to 512GB with performance grades reaching 3.0 TB/s over UCIe, with Google and Tenstorrent joining the standardization work. For RamTrend, the notable point is that NAND vendors are trying to create a memory-adjacent category for AI model weights and long-context data. If adopted, HBF could create new premium demand for high-performance NAND while complementing rather than replacing HBM.