Live RAM price charts, deals, and news signals.

Global NAND revenue increased 70% in the second quarter of 2026 after a 90% increase in the first quarter, according to Counterpoint Research data cited by TechPowerUp. The source attributes the expansion primarily to higher pricing, with NAND contract prices rising 55% sequentially during the quarter. Samsung led the market with 28% revenue share, followed by SK hynix at 19% and Micron at 15%, while YMTC reached 14%. The report links the tight market to AI infrastructure demand for high-capacity enterprise flash, which has encouraged suppliers to prioritize higher-margin data-center products over client SSD capacity. The market-share figures are revenue-based and should not be interpreted as shipment shares.

Micron's 6600 ION places 245TB of QLC NAND in one enterprise SSD, and StorageReview's analysis frames its value around data-center power and floor space rather than raw capacity alone. In the publication's test configuration, one drive replaced eight 30TB nearline hard drives. The SSD system consumed 170.2W during sequential writes, compared with 173.5W for the hard-drive configuration at idle. StorageReview estimates that replacing disk with flash at exabyte scale could reduce a best-case footprint from 22 racks to six and free enough power from fewer than three racks of drives to operate a GB200 NVL72. The figures are workload-specific lab measurements, but they illustrate why ultra-dense QLC flash is becoming an AI-infrastructure planning tool.

Nvidia has announced a $3.5 billion investment in MediaTek and a deeper collaboration around NVLink Fusion, according to TechPowerUp. MediaTek already designed the GB10 system-on-chip used in Nvidia's RTX Spark and DGX Spark systems. Under the expanded relationship, MediaTek plans to offer NVLink Fusion to its ASIC customers, allowing non-Nvidia processors and accelerators to connect to the scale-up fabric through copper or photonic interconnects. TechPowerUp also reports that the arrangement will include access to Nvidia's NVHBM architecture, which places the memory controller in the HBM stack. The collaboration broadens the potential market for custom XPU designs that use Nvidia interconnect and memory technology.

XCENA presented its MX1 memory-centric computing architecture at Hot Chips 2026, according to StorageNewsletter. The company describes a single CXL Type 3 device that combines up to 2TB of DDR5 memory, SSD-backed capacity, and more than 1,000 RISC-V cores. In selected data-analytics kernels, XCENA reported up to 4.7 times the throughput and 18.7 times the energy efficiency of host-CPU processing over CXL. The design aims to reduce data movement between processors and large memory pools, a growing constraint in AI infrastructure. The performance figures are vendor benchmarks on selected workloads, not broad system measurements.

CXMT reached a 10% share of global DRAM revenue in the second quarter of 2026, according to Counterpoint Research figures cited by TechPowerUp. The report says this was up from 8% in the first quarter and represented a substantial increase from a year earlier. Samsung remained the largest supplier at 38%, followed by SK hynix at 25% and Micron at 24%, while Nanya held 2%. The figures point to CXMT gaining commercial traction during a strong memory cycle even as the company faces more limited access to advanced manufacturing equipment than the three largest global suppliers. Market-share estimates should be read as revenue share, not as a direct measure of shipment volume or technology parity.

SK hynix says the bottleneck in AI is moving beyond headline GPU throughput toward the movement of data between memory and compute. In a company-hosted article by KAIST professor Hoi-Jun Yoo, the shift from training toward low-latency inference and agentic workloads is described as increasing repeated memory accesses and the need to retain longer contexts. The analysis argues that accelerator performance cannot be realized when required data arrives too slowly, reviving the long-standing memory-wall problem. It is a technology perspective rather than a product announcement, but it reinforces why HBM, memory hierarchy, data locality, and efficient interconnects are becoming strategic parts of AI infrastructure.

Kioxia's CM9-R is the company's first enterprise SSD family based on eighth-generation BiCS flash, according to StorageReview. The reviewed 15.36TB E3.S model delivered up to 3.4 million random-read IOPS and 14.8 GB/s sequential-read performance while carrying a typical active power rating of 25W. Enterprise Gen5 SSDs are increasingly judged not only by peak throughput but also by how much of that performance they retain at low queue depths, where many real data-center applications operate. The product is a technology and performance update rather than a new market-wide supply or price signal.

Samsung has outlined a performance goal of roughly 4 TB/s for each HBM5 stack in the 2028-2029 period, according to Tom's Hardware. The company expects the generation to deliver twice the performance of HBM4E and a 20% improvement in performance per watt. Samsung has also discussed a heat-path block intended to lower thermal resistance by 20%. The final JEDEC interface is not established in the source. Tom's Hardware calculates that the bandwidth target could require doubling the 2,048-bit HBM4 interface, increasing per-pin transfer rates, or combining both changes. If accelerators eventually carry 20 to 24 stacks, aggregate bandwidth could approach 80 to 96 TB/s, but those package configurations remain roadmap projections.

Hybrid bonding is advancing in logic products, but its expected entry into high-bandwidth memory has moved later. Tom's Hardware reports that a JEDEC decision to permit taller HBM stacks allows HBM4 to retain established microbump connections, leaving HBM4E and HBM5 as the likely first major memory generations to adopt direct copper bonding near the end of the decade. Hybrid bonding can provide much denser vertical connections and reduce stack height, but HBM requires die-to-wafer placement of known-good memory dies. That process is slower and especially sensitive to alignment, surface flatness, and contamination. The revised schedule reduces immediate manufacturing risk for HBM4 while preserving hybrid bonding as an important packaging transition for later stacks.

Cerebras presented a two-generation accelerator roadmap at Hot Chips 2026 that includes its first attempt to stack DRAM over a wafer-scale processor. The company says the CS-6 system's engine will combine a logic-and-SRAM wafer with vertically integrated DRAM, addressing capacity pressure from larger AI models and longer inference contexts. Cerebras currently fills the wafer area with compute and on-chip memory, so adding capacity within the same plane would displace other resources. Moving DRAM into a stacked structure could ease that constraint and reduce the area required by the overall design. The product remains two generations away, and the source does not identify a memory supplier or production schedule.