All published memory-market news.

Nvidia has announced a $3.5 billion investment in MediaTek and a deeper collaboration around NVLink Fusion, according to TechPowerUp. MediaTek already designed the GB10 system-on-chip used in Nvidia's RTX Spark and DGX Spark systems. Under the expanded relationship, MediaTek plans to offer NVLink Fusion to its ASIC customers, allowing non-Nvidia processors and accelerators to connect to the scale-up fabric through copper or photonic interconnects. TechPowerUp also reports that the arrangement will include access to Nvidia's NVHBM architecture, which places the memory controller in the HBM stack. The collaboration broadens the potential market for custom XPU designs that use Nvidia interconnect and memory technology.

XCENA presented its MX1 memory-centric computing architecture at Hot Chips 2026, according to StorageNewsletter. The company describes a single CXL Type 3 device that combines up to 2TB of DDR5 memory, SSD-backed capacity, and more than 1,000 RISC-V cores. In selected data-analytics kernels, XCENA reported up to 4.7 times the throughput and 18.7 times the energy efficiency of host-CPU processing over CXL. The design aims to reduce data movement between processors and large memory pools, a growing constraint in AI infrastructure. The performance figures are vendor benchmarks on selected workloads, not broad system measurements.

CXMT reached a 10% share of global DRAM revenue in the second quarter of 2026, according to Counterpoint Research figures cited by TechPowerUp. The report says this was up from 8% in the first quarter and represented a substantial increase from a year earlier. Samsung remained the largest supplier at 38%, followed by SK hynix at 25% and Micron at 24%, while Nanya held 2%. The figures point to CXMT gaining commercial traction during a strong memory cycle even as the company faces more limited access to advanced manufacturing equipment than the three largest global suppliers. Market-share estimates should be read as revenue share, not as a direct measure of shipment volume or technology parity.

SK hynix says the bottleneck in AI is moving beyond headline GPU throughput toward the movement of data between memory and compute. In a company-hosted article by KAIST professor Hoi-Jun Yoo, the shift from training toward low-latency inference and agentic workloads is described as increasing repeated memory accesses and the need to retain longer contexts. The analysis argues that accelerator performance cannot be realized when required data arrives too slowly, reviving the long-standing memory-wall problem. It is a technology perspective rather than a product announcement, but it reinforces why HBM, memory hierarchy, data locality, and efficient interconnects are becoming strategic parts of AI infrastructure.

Kioxia's CM9-R is the company's first enterprise SSD family based on eighth-generation BiCS flash, according to StorageReview. The reviewed 15.36TB E3.S model delivered up to 3.4 million random-read IOPS and 14.8 GB/s sequential-read performance while carrying a typical active power rating of 25W. Enterprise Gen5 SSDs are increasingly judged not only by peak throughput but also by how much of that performance they retain at low queue depths, where many real data-center applications operate. The product is a technology and performance update rather than a new market-wide supply or price signal.

Samsung has outlined a performance goal of roughly 4 TB/s for each HBM5 stack in the 2028-2029 period, according to Tom's Hardware. The company expects the generation to deliver twice the performance of HBM4E and a 20% improvement in performance per watt. Samsung has also discussed a heat-path block intended to lower thermal resistance by 20%. The final JEDEC interface is not established in the source. Tom's Hardware calculates that the bandwidth target could require doubling the 2,048-bit HBM4 interface, increasing per-pin transfer rates, or combining both changes. If accelerators eventually carry 20 to 24 stacks, aggregate bandwidth could approach 80 to 96 TB/s, but those package configurations remain roadmap projections.

Hybrid bonding is advancing in logic products, but its expected entry into high-bandwidth memory has moved later. Tom's Hardware reports that a JEDEC decision to permit taller HBM stacks allows HBM4 to retain established microbump connections, leaving HBM4E and HBM5 as the likely first major memory generations to adopt direct copper bonding near the end of the decade. Hybrid bonding can provide much denser vertical connections and reduce stack height, but HBM requires die-to-wafer placement of known-good memory dies. That process is slower and especially sensitive to alignment, surface flatness, and contamination. The revised schedule reduces immediate manufacturing risk for HBM4 while preserving hybrid bonding as an important packaging transition for later stacks.

Cerebras presented a two-generation accelerator roadmap at Hot Chips 2026 that includes its first attempt to stack DRAM over a wafer-scale processor. The company says the CS-6 system's engine will combine a logic-and-SRAM wafer with vertically integrated DRAM, addressing capacity pressure from larger AI models and longer inference contexts. Cerebras currently fills the wafer area with compute and on-chip memory, so adding capacity within the same plane would displace other resources. Moving DRAM into a stacked structure could ease that constraint and reduce the area required by the overall design. The product remains two generations away, and the source does not identify a memory supplier or production schedule.

Prices for Nvidia's revived GeForce RTX 3060 12GB have increased sharply since the card returned in late June, according to a survey by Tom's Hardware. Several models now list between $460 and $500 in the United States, with comparable increases also visible in Europe. The card uses older GDDR6 memory and Samsung's 8nm process, both of which should be less constrained than the components in newer GPUs. Even so, retail pricing has reached the level of the faster RTX 5060. The result is a consumer-market signal rather than a direct DRAM contract-price measure, but it suggests that additional availability of an older 12GB design has not translated into lower graphics-card prices.

The combined revenue of the top five enterprise SSD suppliers is projected to reach $37.59 billion in the second quarter of 2026, according to a TrendForce report carried by TechPowerUp. That would represent a 103.6% sequential increase, supported by higher contract prices and increased unit shipments. Demand is expected to remain strong in the third quarter as cloud providers expand data centers, generative-AI agent services gain adoption, and Nvidia GB-series server racks ship at scale. TrendForce also points to rising Chinese output and growth in China's domestic cloud market as factors that could alter the vendor landscape.

SK hynix says AI performance increasingly depends on the complete path that supplies data to accelerators, rather than GPU speed alone. The company cites research showing that server compute capability has advanced substantially faster than DRAM and interconnect bandwidth over the past two decades. As that imbalance grows, accelerators can spend more time waiting for data, reducing system efficiency. The analysis supports continued demand for higher-bandwidth memory and better integration among compute, networking, and storage, although it does not announce a product or a production target.

The 1TB Kingston NV3 is listed at $156.99 in a Newegg promotion reported by Tom's Hardware, down from a usual price of $215.99. That equals 15.7 cents per gigabyte and is described as the drive's lowest price in 30 days. The offer provides a short-lived consumer value point, but it does not demonstrate a broader decline in NAND or SSD prices.

SK hynix CEO Kwak Noh-Jung expects the current memory shortage to continue through the end of 2030, according to a report citing Reuters. He argues that customized DRAM and HBM for AI systems make demand more predictable and less exposed to the abrupt oversupply cycles that previously caused price crashes. The statement extends the company's earlier expectation of tight commodity DRAM supply through 2028.

CXMT DDR5 chips reportedly operated stably at 8,000 MT/s in a comparison with current SK hynix memory. DigiTimes says measured application and gaming performance differed by about one percent or less. A narrow benchmark gap suggests faster progress in high-speed Chinese DRAM, although broader conclusions still depend on yields, power, reliability and production scale.

Samsung and SK hynix are pursuing different approaches to improve HBM system performance, DigiTimes reports. Samsung presents processing-in-memory as a way to reduce movement between compute and memory, while SK hynix is prioritizing packaging and interconnect development. The contrast shows that future HBM gains may depend as much on architecture and integration as on DRAM speed.

Apple is negotiating lower OLED panel prices with suppliers in South Korea, according to DigiTimes. The report says higher costs for performance-oriented mobile DRAM, NAND Flash and other memory components are weighing on gross margin. Offering larger display orders in return for discounts suggests device makers are trying to offset memory inflation elsewhere in the bill of materials.

Micron is investigating a tightly coupled DRAM architecture intended to narrow the growing gap between processor throughput and memory bandwidth. DigiTimes reports that the concept targets more than ten times current HBM bandwidth with substantially lower energy consumption per transferred bit. The work signals a possible direction beyond today's packaging model, but the supplied material gives no production schedule or commercial specifications.

ASRock has added the B550M Pro-A WiFi 6E, a microATX motherboard for AMD's long-running AM4 platform. The board provides four DDR4 DIMM slots with overclocked memory support up to DDR4-4733+, and the report expects pricing near $90 without a confirmed MSRP. New AM4 designs show how mature DDR4 ecosystems can remain attractive when newer memory carries a substantial cost premium.

Tom's Hardware reports a 35% discount on Corsair's 32GB DDR5-6000 Vengeance kit, reducing the price by $215. The promotion temporarily places the kit below other 32GB products at the same data rate. Because the report also notes shrinking stock and continuing price increases, the deal appears to be an isolated retail opportunity rather than evidence of a broad market decline.

A technical whitepaper highlighted by Semiconductor Engineering focuses on bringing high-fidelity thermal analysis into the floorplanning stage of 2.5D package design. The method is intended to identify hotspots, manage rising power density and co-optimize dies and packaging within limited thermal budgets. Earlier feedback may help designers evaluate HBM placement and cooling tradeoffs before layouts become expensive to change.