All published memory-market news.

StorageReview reports that Amazon Web Services has launched the R9g and R9gd instance families based on Graviton5 processors. The Arm-based systems target databases, in-memory caches, analytics, containers and microservices that benefit from high memory bandwidth. AWS says the new instances can deliver up to 25% higher per-vCPU compute performance than the prior Graviton4 R8g family. The platform raises memory speed from DDR5-5600 to DDR5-8800 MT/s and increases L3 cache capacity fivefold. On the largest r9g.48xlarge configuration, AWS lists up to 100 Gbps of network bandwidth and 72 Gbps of Amazon EBS bandwidth. The launch is a demand-side signal for faster server DDR5 platforms. It does not disclose memory volumes or purchasing plans, so its direct effect on DRAM pricing is unclear.

DigiTimes reports that AI infrastructure spending continued to lift demand for both conventional DRAM and high-bandwidth memory during the second quarter of 2026. The publication says Samsung regained the leading position in the DRAM market while China's CXMT increased its presence. The combination of stronger AI demand and broader supplier participation illustrates two forces shaping the market at once: high-value HBM requirements are expanding, while Chinese producers are seeking a larger role in the broader DRAM landscape. The supplied report provides no market-share or pricing figures. It supports a view of firm AI-related demand, but does not by itself establish a near-term direction for DRAM prices.

Montage Technology is moving beyond its traditional DDR memory-interface business with CXL 3.2, DDR6 and PCIe products aimed at AI data-center infrastructure, according to DigiTimes. The publication says the Chinese interconnect chipmaker has entered CXL 3.2 supply chains connected to Samsung and SK hynix. The move highlights how memory-interface and interconnect vendors are preparing for systems that combine faster DDR generations with pooled and expandable memory. CXL can allow compute platforms to attach and share memory resources more flexibly, while DDR6 development points to the next generation of server-memory interfaces. The supplied report does not specify the products, volumes or qualification dates involved. Its immediate price impact is therefore unclear, but it is relevant to the developing ecosystem around future server memory.

DigiTimes reports that Micron is targeting approximately 100,000 HBM wafers per month by the end of 2026, which would represent roughly twice its current high-bandwidth-memory capacity. The report also says the company plans a substantial increase in 12-high HBM4 output for NVIDIA's Vera Rubin AI platform. Samsung and SK hynix retain a scale advantage in HBM, according to the report. If Micron reaches the stated capacity target, the industry would have a larger pool of supply for advanced AI memory. The supplied source does not provide a commissioning schedule, customer volumes or independent confirmation of the capacity plan. It should therefore be treated as a reported target rather than a completed expansion.

According to DigiTimes, Kioxia is advancing a strategy to use flash memory in roles that have historically relied on DRAM. The report frames the effort against Kioxia's position as a major NAND supplier without its own DRAM manufacturing business. The same report says Kioxia faces stronger competition from Micron and China's YMTC in flash. Moving more workloads toward flash could help the company differentiate its product strategy, but the supplied report does not provide product specifications, deployment timelines or customer commitments. The development is therefore best viewed as a strategic direction rather than a confirmed near-term shift in DRAM demand or pricing. Any market effect will depend on technical adoption and the economics of the targeted workloads.

EE Times Asia reports that Marvell is presenting three product lines as parts of one memory-disaggregation approach: the Bravera SC6 PCIe 6.0 SSD controller, Structera CXL products for memory expansion and pooling, and Photonic Fabric components for optical shared-memory designs. The company positions the portfolio across server storage, rack-scale memory pooling and multi-rack shared-memory architectures. In the storage layer, the Bravera controller is intended for AI-oriented workloads such as key-value caching, where placing more data on SSDs can improve infrastructure efficiency. For memory markets, the significance is architectural rather than an immediate supply event. Wider deployment of CXL and SSD-backed data tiers could alter how hyperscalers allocate DDR memory and NAND capacity as AI clusters scale.

TrendForce data cited by EE Times Asia puts the quarter-on-quarter increase in combined revenue for the five leading enterprise SSD vendors at 103.6%. The report attributes the growth to higher shipments and contract prices as cloud operators expand AI infrastructure. Samsung led the group with about $14.35 billion in revenue, followed by SK hynix Group at more than $8.63 billion. Micron recorded the fastest growth, rising 126.3% from the prior quarter to roughly $6.98 billion. Kioxia generated about $4.64 billion and SanDisk nearly $2.98 billion. The report expects enterprise SSD demand to remain strong in the third quarter, supported by generative-AI services, continued cloud deployment and shipments of NVIDIA GB-series server racks. The growing role of high-capacity QLC drives and newer PCIe products points to sustained demand for enterprise NAND, although additional Chinese supply and domestic cloud demand could change the competitive balance over time.

Global NAND revenue increased 70% in the second quarter of 2026 after a 90% increase in the first quarter, according to Counterpoint Research data cited by TechPowerUp. The source attributes the expansion primarily to higher pricing, with NAND contract prices rising 55% sequentially during the quarter. Samsung led the market with 28% revenue share, followed by SK hynix at 19% and Micron at 15%, while YMTC reached 14%. The report links the tight market to AI infrastructure demand for high-capacity enterprise flash, which has encouraged suppliers to prioritize higher-margin data-center products over client SSD capacity. The market-share figures are revenue-based and should not be interpreted as shipment shares.

Micron's 6600 ION places 245TB of QLC NAND in one enterprise SSD, and StorageReview's analysis frames its value around data-center power and floor space rather than raw capacity alone. In the publication's test configuration, one drive replaced eight 30TB nearline hard drives. The SSD system consumed 170.2W during sequential writes, compared with 173.5W for the hard-drive configuration at idle. StorageReview estimates that replacing disk with flash at exabyte scale could reduce a best-case footprint from 22 racks to six and free enough power from fewer than three racks of drives to operate a GB200 NVL72. The figures are workload-specific lab measurements, but they illustrate why ultra-dense QLC flash is becoming an AI-infrastructure planning tool.

Nvidia has announced a $3.5 billion investment in MediaTek and a deeper collaboration around NVLink Fusion, according to TechPowerUp. MediaTek already designed the GB10 system-on-chip used in Nvidia's RTX Spark and DGX Spark systems. Under the expanded relationship, MediaTek plans to offer NVLink Fusion to its ASIC customers, allowing non-Nvidia processors and accelerators to connect to the scale-up fabric through copper or photonic interconnects. TechPowerUp also reports that the arrangement will include access to Nvidia's NVHBM architecture, which places the memory controller in the HBM stack. The collaboration broadens the potential market for custom XPU designs that use Nvidia interconnect and memory technology.

XCENA presented its MX1 memory-centric computing architecture at Hot Chips 2026, according to StorageNewsletter. The company describes a single CXL Type 3 device that combines up to 2TB of DDR5 memory, SSD-backed capacity, and more than 1,000 RISC-V cores. In selected data-analytics kernels, XCENA reported up to 4.7 times the throughput and 18.7 times the energy efficiency of host-CPU processing over CXL. The design aims to reduce data movement between processors and large memory pools, a growing constraint in AI infrastructure. The performance figures are vendor benchmarks on selected workloads, not broad system measurements.

CXMT reached a 10% share of global DRAM revenue in the second quarter of 2026, according to Counterpoint Research figures cited by TechPowerUp. The report says this was up from 8% in the first quarter and represented a substantial increase from a year earlier. Samsung remained the largest supplier at 38%, followed by SK hynix at 25% and Micron at 24%, while Nanya held 2%. The figures point to CXMT gaining commercial traction during a strong memory cycle even as the company faces more limited access to advanced manufacturing equipment than the three largest global suppliers. Market-share estimates should be read as revenue share, not as a direct measure of shipment volume or technology parity.

SK hynix says the bottleneck in AI is moving beyond headline GPU throughput toward the movement of data between memory and compute. In a company-hosted article by KAIST professor Hoi-Jun Yoo, the shift from training toward low-latency inference and agentic workloads is described as increasing repeated memory accesses and the need to retain longer contexts. The analysis argues that accelerator performance cannot be realized when required data arrives too slowly, reviving the long-standing memory-wall problem. It is a technology perspective rather than a product announcement, but it reinforces why HBM, memory hierarchy, data locality, and efficient interconnects are becoming strategic parts of AI infrastructure.

Kioxia's CM9-R is the company's first enterprise SSD family based on eighth-generation BiCS flash, according to StorageReview. The reviewed 15.36TB E3.S model delivered up to 3.4 million random-read IOPS and 14.8 GB/s sequential-read performance while carrying a typical active power rating of 25W. Enterprise Gen5 SSDs are increasingly judged not only by peak throughput but also by how much of that performance they retain at low queue depths, where many real data-center applications operate. The product is a technology and performance update rather than a new market-wide supply or price signal.

Samsung has outlined a performance goal of roughly 4 TB/s for each HBM5 stack in the 2028-2029 period, according to Tom's Hardware. The company expects the generation to deliver twice the performance of HBM4E and a 20% improvement in performance per watt. Samsung has also discussed a heat-path block intended to lower thermal resistance by 20%. The final JEDEC interface is not established in the source. Tom's Hardware calculates that the bandwidth target could require doubling the 2,048-bit HBM4 interface, increasing per-pin transfer rates, or combining both changes. If accelerators eventually carry 20 to 24 stacks, aggregate bandwidth could approach 80 to 96 TB/s, but those package configurations remain roadmap projections.

Hybrid bonding is advancing in logic products, but its expected entry into high-bandwidth memory has moved later. Tom's Hardware reports that a JEDEC decision to permit taller HBM stacks allows HBM4 to retain established microbump connections, leaving HBM4E and HBM5 as the likely first major memory generations to adopt direct copper bonding near the end of the decade. Hybrid bonding can provide much denser vertical connections and reduce stack height, but HBM requires die-to-wafer placement of known-good memory dies. That process is slower and especially sensitive to alignment, surface flatness, and contamination. The revised schedule reduces immediate manufacturing risk for HBM4 while preserving hybrid bonding as an important packaging transition for later stacks.

Cerebras presented a two-generation accelerator roadmap at Hot Chips 2026 that includes its first attempt to stack DRAM over a wafer-scale processor. The company says the CS-6 system's engine will combine a logic-and-SRAM wafer with vertically integrated DRAM, addressing capacity pressure from larger AI models and longer inference contexts. Cerebras currently fills the wafer area with compute and on-chip memory, so adding capacity within the same plane would displace other resources. Moving DRAM into a stacked structure could ease that constraint and reduce the area required by the overall design. The product remains two generations away, and the source does not identify a memory supplier or production schedule.

Prices for Nvidia's revived GeForce RTX 3060 12GB have increased sharply since the card returned in late June, according to a survey by Tom's Hardware. Several models now list between $460 and $500 in the United States, with comparable increases also visible in Europe. The card uses older GDDR6 memory and Samsung's 8nm process, both of which should be less constrained than the components in newer GPUs. Even so, retail pricing has reached the level of the faster RTX 5060. The result is a consumer-market signal rather than a direct DRAM contract-price measure, but it suggests that additional availability of an older 12GB design has not translated into lower graphics-card prices.

The combined revenue of the top five enterprise SSD suppliers is projected to reach $37.59 billion in the second quarter of 2026, according to a TrendForce report carried by TechPowerUp. That would represent a 103.6% sequential increase, supported by higher contract prices and increased unit shipments. Demand is expected to remain strong in the third quarter as cloud providers expand data centers, generative-AI agent services gain adoption, and Nvidia GB-series server racks ship at scale. TrendForce also points to rising Chinese output and growth in China's domestic cloud market as factors that could alter the vendor landscape.

SK hynix says AI performance increasingly depends on the complete path that supplies data to accelerators, rather than GPU speed alone. The company cites research showing that server compute capability has advanced substantially faster than DRAM and interconnect bandwidth over the past two decades. As that imbalance grows, accelerators can spend more time waiting for data, reducing system efficiency. The analysis supports continued demand for higher-bandwidth memory and better integration among compute, networking, and storage, although it does not announce a product or a production target.