All published memory-market news.

Nvidia and SK Group signed letters of intent covering a strategic relationship valued at more than $500 billion over multiple activities and years. The announcement ties together a previously disclosed long-term memory supply and co-development agreement with SK hynix, a planned 2 GW AI data center from SK Telecom in South Korea, and additional future AI infrastructure expansion. The planned data center is expected to use Nvidia's DSX AI factory platform and Vera Rubin systems paired with SK hynix HBM4 memory, with first service targeted for 2027. While the total partnership value appears to include hardware, infrastructure, and ecosystem spending beyond memory alone, the deal still matters for RamTrend because it reinforces long-horizon demand for high-bandwidth memory in large AI deployments. That points to firm support for premium memory supply allocation, even if the source does not quantify exact memory volumes.

Tom's Hardware highlighted Game Compressor, a Windows-based utility that applies built-in LZX compression to installed games in order to reduce storage use. Reported examples include a reduction in ARK: Survival Evolved from 169 GB to 91 GB and a 32 GB cut for Crimson Desert, though savings vary by title. The article argues that elevated SSD pricing, with entry 2 TB drives nearing $250 and faster models costing more, is making software-based space management more appealing. For RamTrend, the main takeaway is not the utility itself but the market context: when NAND and SSD prices remain high, buyers are more likely to delay capacity upgrades and rely on compression, recompression after patches, or other workarounds.

SK Group and NVIDIA said they are expanding their strategic cooperation across AI infrastructure, with the memory angle centered on a long-term partnership between NVIDIA and SK hynix. The companies said NVIDIA will secure more stable access to next-generation AI memory while the two sides work together on future HBM solutions. The announcement also ties that memory roadmap to a planned 2-gigawatt AI cloud project in Korea using NVIDIA Vera Rubin systems and SK hynix HBM4, with the first AI factory targeted for 2027. For the memory market, the announcement matters less as a near-term pricing event than as a supply signal. It reinforces how AI infrastructure rollouts are driving demand visibility for advanced memory, especially HBM, and it suggests large customers want deeper supply commitments rather than relying on spot availability. That supports the strategic position of SK hynix in premium AI memory, even though the release does not quantify shipment volumes, pricing terms, or exact capacity commitments.

Supply-chain commentary indicates the recent NAND upswing is moving into a steadier phase instead of breaking lower. The latest view is that prices have reached a high plateau in the second half of 2026, with restricted supply continuing to support the market even as rising procurement costs reduce some spot-market activity. That combination matters because softer spot demand alone may not be enough to push prices down if available supply remains constrained. For SSD vendors, OEM buyers, and storage channel participants, the near-term implication is continued cost pressure and limited pricing relief rather than a clear downturn.

Reuters figures cited by TechPowerUp indicate that CXMT has moved above Samsung in pricing for 64 GB DDR5 server RDIMMs, with Samsung already at about $1,240 per module. The reported shift suggests that demand for server memory has risen enough to remove the pricing advantage many expected from CXMT. The article says demand has increased roughly tenfold and that Chinese electronics firms have complained to regulators about price increases from both CXMT and YMTC, arguing that higher component costs are delaying product launches. That strengthens the view that supply remains constrained across key memory categories. CXMT is also expanding aggressively, with two new plants under construction in Shanghai and Hefei and discussions around a third fab. If those projects come online as planned, the company’s monthly wafer capacity would exceed 600,000, more than doubling current output. In the near term, though, the pricing signal matters more than the expansion plan: current availability appears tight enough that even a fast-growing DRAM supplier can raise prices instead of discounting.

Gigabyte has announced official support for DDR5 modules built with CXMT chips across select Socket AM5 and LGA1851 motherboards. In the company’s example, a pair of 16GB Lexar modules using CXMT memory reached 8200 MT/s on a B850M FORCE board alongside a Ryzen 5 8600G, with reported AIDA64 latency of 65.4ns. The announcement matters because motherboard validation helps move CXMT memory closer to mainstream compatibility, not just isolated China-market tuning efforts. Gigabyte also said support covers modules using 16Gb and 24Gb ICs, which maps to common 16GB, 24GB, 32GB, and 48GB capacities. For the memory market, the main implication is supply diversification. If CXMT-based modules become easier to qualify and ship at scale, they could add competitive pressure in consumer DDR5. The near-term effect is limited by uncertain availability outside China and by geopolitical risk around future US restrictions.

A new hiring push in Silicon Valley indicates SK hynix is building closer design ties with US customers around 3D stacked DRAM-on-logic architectures. Based on the source description, the effort extends the company’s custom memory strategy beyond high-bandwidth memory and points toward memory solutions for on-device AI applications. For the memory market, the development matters less as an immediate pricing catalyst and more as a sign that advanced DRAM integration is becoming a competitive design priority outside the traditional HBM segment.

AMD has shared its first substantial Venice roadmap details around the 256-core EPYC 9996 and related server designs, and the memory story is one of the clearest takeaways. On the SP7 platform, AMD says Venice can reach 1.6 TB/s of per-socket memory bandwidth with fast MRDIMMs, while also supporting standard DDR5 RDIMMs at 8000 MT/s. The company says this is a step up from Turin's 12-channel platform and positions Venice for data-intensive and AI-oriented workloads. AMD also outlined a second design direction with Verano, an AI host node that it says will use a 24-channel LPDDR5X memory system based on SOCAMM2 modules. Taken together, the roadmap suggests server vendors will keep experimenting with both traditional high-bandwidth DIMM configurations and more specialized low-power memory topologies as AI infrastructure requirements diversify.

A wave of coordinated protests across 42 U.S. states has highlighted rising resistance to large data center projects, while local and state restrictions continue to slow or block new builds. The source reports that 142 protest events were held and says more than 69 jurisdictions have already imposed some form of data center ban or moratorium, with over $130 billion in projects delayed during early 2026. For RamTrend, the main significance is timing. AI data centers are major future buyers of server memory and storage, so permitting delays can push back deployment schedules for DRAM- and NAND-heavy systems even if long-term demand remains intact. This does not signal a collapse in memory demand, but it does add another bottleneck alongside power, infrastructure, and chip availability.

Framework has revised pricing and fulfillment plans for its upcoming Laptop 13 Pro after receiving a sharply higher LPCAMM2 memory quote from its supplier. According to the company, the new pricing was more than double the cost of earlier inventory, pushing Framework to raise future preorder prices for 32GB and 64GB configurations while reshuffling some existing orders to lower-capacity modules at original price points. The article says 32GB LPCAMM2 pricing moved to $800 from $439, while 64GB rose to $1,600 from $849, and that additional system and mainboard increases are also tied to higher memory, storage, and other silicon costs. Framework also pointed to mixed moves in adjacent components, with some DDR5 and SSD options becoming cheaper and others more expensive. For RamTrend, this is concrete evidence that memory-market volatility is flowing through to OEM pricing, product mix decisions, and customer-facing availability.

BloombergNEF has sharply increased its forecast for U.S. data center electricity demand, lifting its 2035 estimate to 194 GW from 106 GW in its December outlook. The report says data centers could account for roughly 20% of U.S. electricity use by 2035 and still face a 19 GW supply gap even if grid connection activity stays at a record pace. The revised forecast reflects the growing pipeline of AI facilities rather than only projects already under construction, and the article also notes that delays, cancellations, and long transformer lead times remain constraints. For RamTrend, the signal is that AI infrastructure demand is still expanding, which can support medium-term demand for server memory, although the power and grid bottlenecks may slow how quickly that demand converts into deployed hardware.

The effects of the current memory shortage are spreading further into the automotive industry. According to the source, General Motors now expects company costs to rise by $1.5 billion to $2 billion, with increasing component prices led in part by DRAM, while BYD has raised driver-assistance feature pricing by 20%. Hyundai is also calling for stronger domestic chip supply support. The story matters because modern vehicles are becoming materially more memory-intensive. The source cites Micron's earlier estimate that average vehicle DRAM and NAND usage would climb from 90GB in 2023 to 278GB by 2026, with some high-end models reaching far higher totals. Infotainment, safety systems, centralized compute, and future in-car AI assistants are all adding to memory requirements, which makes the auto sector more exposed to shortages in specialized chips. For the memory market, this is a sign that constrained supply is affecting a broader set of end markets. Automotive memory uses parts that require long validation cycles and cannot always be replaced quickly with standard supply. That raises the risk of persistent pricing pressure, delayed vehicle deliveries, and stronger competition for DRAM and NAND output across consumer, enterprise, and industrial demand.

AMD introduced its 6th Gen EPYC "Venice" server processors, splitting the lineup across multiple product tiers for mainstream servers, enterprise deployments, HPC, and AI host nodes. For memory-market watchers, the most important detail is the upgraded memory subsystem rather than the CPU core counts alone. According to the source, Socket SP7 versions support a 16-channel DDR5 interface with native DDR5-8000 RDIMMs and MRDIMM support up to DDR5-12800. AMD also disclosed LPDDR5X-based EPYC 9006 LP "Verano" variants with 24-channel interfaces and support for field-replaceable SOCAMM2 modules. Those specifications indicate a push toward higher memory bandwidth and more specialized memory footprints for server and AI platforms. The market implication is constructive for premium server-memory demand. Faster DDR5 server modules and LPDDR5X configurations for AI host nodes can support more differentiated platform designs, especially where memory throughput and density are critical. While this is not the same kind of supply shock as a major HBM announcement, it still points to continued upward pressure on advanced server-memory adoption.

AMD disclosed new technical details for its upcoming MI455X accelerator, built on its CDNA 5 architecture and paired with the Helios rack-scale design. The company says a single MI455X integrates 12 stacks of HBM4 for 432GB of capacity and 23.3 TB/s of bandwidth, while a 72-GPU Helios configuration brings that memory into a single coherent domain. The memory subsystem is one of the most important takeaways for RamTrend readers. AMD is framing the product as a higher-capacity option than Nvidia's initially described Rubin configuration, which the source says offers 288GB of HBM4 and up to 22 TB/s per GPU. If those specifications translate into shipping systems, hyperscalers and AI platform buyers will keep pushing demand toward premium HBM supply, advanced packaging capacity, and closely coupled compute-memory designs. The report also highlights AMD's use of advanced chiplet packaging, hybrid bonding, and TSMC CoWoS-L integration. That combination reinforces a broader market pattern: AI accelerators are no longer competing only on compute throughput, but also on memory bandwidth, capacity per accelerator, and packaging scale. For the memory market, that is supportive of continued strategic importance for HBM4 and related supply-chain investments.

AMD said its Venice server CPU family will scale to 256 cores and deliver up to 1.6TB/s of memory bandwidth, while also supporting PCIe Gen 6 and multiple platform variants across general-purpose, host-node, and dense compute use cases. The source also describes Verano as an LPDDR-based host option and notes that higher-speed MRDIMM configurations can materially improve some HPC results versus standard RDIMM setups. For memory markets, the practical takeaway is that server platform competition is increasingly tied to memory throughput and configuration flexibility, not only raw CPU core counts. That supports ongoing demand for higher-performance DDR5 server modules, MRDIMMs, and specialized host memory designs tied to AI infrastructure. The source provides strong product claims but limited hard data on shipment volumes and customer procurement timing, so any direct pricing effect on server DRAM should still be treated as moderate rather than immediate.

AMD said its new MI455X accelerator uses 12 HBM4 stacks for a total of 432GB of memory and 23.3TB/s of bandwidth, and that a full 72-GPU Helios rack aggregates that into roughly 31TB of HBM4. The company presented the platform as a high-scale AI system aimed at hyperscalers and large model operators, with customers such as OpenAI, Meta, Anthropic, Microsoft, and Oracle cited as adopters of Helios. From a memory-market perspective, the key signal is not consumer DRAM but continued escalation in premium AI memory content per accelerator. If deployments move from announcement to volume rollout, demand pressure should stay concentrated around HBM4 supply, advanced packaging, and related server memory configurations in AI infrastructure. The item does not provide shipment volumes or procurement timelines, so near-term pricing effects should be treated as directional rather than confirmed.

A new Semiconductor Engineering report says silicon photonics is advancing toward wider deployment in AI systems, data centers, and communications hardware, but design and verification flows are still immature. The article describes how chip teams must now model not only electronic behavior, but also waveguides, thermal effects, packaging, optical-electrical conversion, and full system interactions. It highlights comments from executives and engineers across Cadence, Synopsys, Siemens EDA, Keysight EDA, Ayar Labs, Baya Systems, and Axiomise, all pointing to the same challenge: photonic devices are becoming part of larger multi-die systems, yet toolchains remain fragmented and physics-heavy. For RamTrend, the article matters because optical I/O and co-packaged optics are being developed to improve bandwidth and power efficiency around AI compute platforms. That does not directly move DRAM or NAND pricing today, but it supports the infrastructure roadmap behind future demand for accelerator memory, high-performance servers, and large-scale data-center builds.

A report cited by Tom's Hardware says Meta may use a custom AMD Instinct MI400-series design with 144GB of HBM4 for selected recommendation workloads. The described configuration is substantially smaller than the 432GB HBM4 setup associated with the full Instinct MI455X-class product, and it would also trim compute capability to match a narrower use case. For RamTrend, the key point is that hyperscale buyers are actively tuning memory capacity and package size to control AI infrastructure costs. Lower HBM content per accelerator can improve cost efficiency for fixed workloads, but it does not reduce the strategic importance of HBM4. Instead, it shows how expensive advanced memory has become and how strongly it shapes accelerator design choices, total cost of ownership, and workload segmentation. If the report is accurate, the immediate effect on memory pricing is mixed. Using less HBM4 per unit would reduce memory content in these specific Meta deployments, yet the broader signal remains supportive for premium memory demand because major AI operators are still designing around HBM-heavy platforms and differentiating products by memory configuration.

NVIDIA published a deeper technical look at its Rubin GPU architecture, describing a high-end accelerator aimed at scaling across racks and data centers. The company said the design can reach 50 petaFLOPS in sparse NVFP4 workloads and pairs the compute complex with 288 GB of HBM4 delivered through 12-high memory stacks. NVIDIA also said Rubin is designed for peak memory bandwidth of up to 22 TB/s, with NVLink 6 and other interconnect upgrades supporting larger system-level deployments. For memory markets, the key takeaway is not immediate spot pricing but the continued push toward higher-capacity, higher-bandwidth HBM configurations for AI infrastructure. That supports long-range demand visibility for premium memory packaging and supply chains tied to advanced accelerators.

Rambus announced two presentations for the D&R IP SoC South Korea event, including one focused on AI inference memory design. In that session, the company argues that inference workloads split into different stages with different bottlenecks, so a single memory approach is inefficient. Rambus says lower-cost GDDR or LPDDR can support prefill workloads, while HBM should be reserved for stages that depend more heavily on bandwidth and latency, with pooled memory used for KV offload. For RamTrend, the key takeaway is not the event itself but the continued push toward mixed memory hierarchies in AI systems, which could shape how future demand is distributed across premium and mainstream memory categories.