RamTrend

AI Infrastructure · Jul 20, 2026

High Bandwidth Flash Emerges as a Lower-Cost Memory Tier for AI Inference

An emerging NAND-based architecture is being positioned as a way to expand AI inference memory capacity without relying entirely on premium HBM. If the concept matures, it could influence how data centers balance bandwidth, cost, and memory hierarchy.

Price impact: 1Direction: neutralSource: IEEE Spectrum Semiconductors

IEEE Spectrum reports that High Bandwidth Flash, or HBF, is being explored as a new memory tier for AI inference workloads. The concept applies advanced stacking and packaging methods to NAND flash so that read bandwidth rises well above conventional storage, while still remaining below the performance level of HBM. According to the source, Sandisk has outlined a first-generation design with up to 16 NAND dies, up to 512 GB per stack, and projected read bandwidth of as much as 1.6 TB/s, with later roadmap targets reaching 2 TB/s and 3.2 TB/s. The rationale is tied to inference rather than training. Because inference keeps model weights largely read-only, a flash-based tier could hold large static data sets while HBM handles faster working memory duties. The article also notes that Sandisk and SK hynix launched a standardization effort for HBF within the Open Compute Project on February 25, 2026, but a publication timeline for the standard has not been set. For the memory market, HBF does not displace HBM in the near term, but it points to a possible future where NAND suppliers gain a larger role in AI server memory architectures.

SandiskSK hynixNAND FlashHBMAI inferenceadvanced packaging
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