V-NAND reliability paper points to charge-trap scaling risks

A new technical paper from researchers at the University of Seoul and Samsung Electronics focuses on reliability behavior inside vertical NAND. The study looks at band-to-band tunneling in the charge-trap layer under demanding erase and program conditions, connecting the effect to charge loss, neighboring-cell disturbance, and early threshold-voltage movement. For RamTrend, this is not a near-term pricing item. Its relevance is that NAND scaling and reliability issues can influence manufacturing complexity, yield learning, and the pace at which denser products reach stable production. The paper reinforces that V-NAND advancement still depends on managing device-level effects, not only adding layers or improving package-level capacity.