Cadence's TSMC design update covers memory interfaces and HBM integration

EE Times Asia reports an expanded Cadence and TSMC collaboration covering advanced processes and multi-die packaging. Cadence's analog, digital and signoff tools have received N2P certification, and DDR5 and LPDDR5 IP have taped out on that process. The article also identifies LPDDR6 IP under development for A14. Packaging support includes HBM logic base dies within larger chiplet assemblies. These developments concern the tools and interfaces used to integrate memory into future compute systems. They do not announce new DRAM factory capacity or an immediate increase in memory-chip supply.