4-high HBM stacks could stretch scarce DRAM capacity for AI inference

SemiAnalysis examines the case for four-high HBM stacks in AI inference hardware. Its analysis argues that a lower-height stack can provide comparable bandwidth in some designs while consuming fewer DRAM dies than taller alternatives. That design choice matters because HBM has become a larger user of global DRAM wafer output as accelerator makers add more and denser memory stacks to AI systems. Reducing the number of dies required per deployed accelerator could allow the same constrained DRAM supply to serve more systems. The analysis is a technical and economic argument rather than an announced product transition, so its effect on the market remains conditional. If adopted broadly, it could improve memory efficiency in inference deployments and moderate the strain on scarce HBM and DRAM resources.