NUS researchers propose heterogeneous memory chiplets for LLM inference

Researchers at the National University of Singapore have presented CHIPSMORE, a proposed accelerator for serving language-model inference requests. Semiconductor Engineering reports that the design combines compute-in-interconnect techniques with compute-in-memory chiplets. The study targets systems that must handle different inference modes and multiple requests at once, including low-rank adaptation workloads. Moving selected operations nearer to memory can reduce data-transfer pressure, which is a central constraint in many AI inference designs. This is research rather than a commercial product announcement, so it does not change current memory demand or pricing. It is nevertheless relevant to the longer-term direction of AI-memory architectures and the ways chiplet integration may be used to improve inference efficiency.