Samsung Targets 4 TB/s per Stack for HBM5

Samsung has outlined a performance goal of roughly 4 TB/s for each HBM5 stack in the 2028-2029 period, according to Tom's Hardware. The company expects the generation to deliver twice the performance of HBM4E and a 20% improvement in performance per watt. Samsung has also discussed a heat-path block intended to lower thermal resistance by 20%. The final JEDEC interface is not established in the source. Tom's Hardware calculates that the bandwidth target could require doubling the 2,048-bit HBM4 interface, increasing per-pin transfer rates, or combining both changes. If accelerators eventually carry 20 to 24 stacks, aggregate bandwidth could approach 80 to 96 TB/s, but those package configurations remain roadmap projections.