Cerebras Plans Stacked DRAM for a Future Wafer-Scale Accelerator

Cerebras presented a two-generation accelerator roadmap at Hot Chips 2026 that includes its first attempt to stack DRAM over a wafer-scale processor. The company says the CS-6 system's engine will combine a logic-and-SRAM wafer with vertically integrated DRAM, addressing capacity pressure from larger AI models and longer inference contexts. Cerebras currently fills the wafer area with compute and on-chip memory, so adding capacity within the same plane would displace other resources. Moving DRAM into a stacked structure could ease that constraint and reduce the area required by the overall design. The product remains two generations away, and the source does not identify a memory supplier or production schedule.