Synopsys CXL 4.0 IP targets faster memory pooling for AI systems

Synopsys introduced a Compute Express Link 4.0 intellectual-property suite that combines controller IP, IDE security blocks, a PCIe 7.0-based physical layer and verification IP. The company says the technology supports 128 GT/s operation and frames the design around AI infrastructure use cases, including faster key-value cache offload compared with SSD-based approaches. The announcement is not a direct component-price event, but it is relevant to memory architecture because CXL is one of the main paths for attaching and pooling larger memory tiers around accelerators and CPUs. If adopted by SoC vendors, the IP could support more systems that use expanded memory fabrics rather than relying only on local DRAM or SSD storage tiers.