Price impact: 2Direction: unclearSource: Tom's Hardware
Tom's Hardware reports that AMD confirmed Venice-X for the second half of 2027. The compact payload lists 96 cores, boost clocks up to 5.15GHz, and 1,152MB of L3 cache through 3D V-Cache. For RamTrend, this is not a DRAM pricing story, but it is relevant to memory hierarchy design. Larger on-package cache can reduce some trips to external memory for cache-sensitive HPC and data-center workloads. That may improve performance per socket, while total platform DRAM demand will still depend on workload size, node count, and deployment volume.
AMD3D V-Cacheserver CPU cachedata-center memory hierarchy
Original sourceBack to news archive