AMD ties next-gen EPYC roadmap to higher memory bandwidth and denser channel counts

AMD has shared its first substantial Venice roadmap details around the 256-core EPYC 9996 and related server designs, and the memory story is one of the clearest takeaways. On the SP7 platform, AMD says Venice can reach 1.6 TB/s of per-socket memory bandwidth with fast MRDIMMs, while also supporting standard DDR5 RDIMMs at 8000 MT/s. The company says this is a step up from Turin's 12-channel platform and positions Venice for data-intensive and AI-oriented workloads. AMD also outlined a second design direction with Verano, an AI host node that it says will use a 24-channel LPDDR5X memory system based on SOCAMM2 modules. Taken together, the roadmap suggests server vendors will keep experimenting with both traditional high-bandwidth DIMM configurations and more specialized low-power memory topologies as AI infrastructure requirements diversify.