Side-stacked DRAM research targets HBM heat and capacity limits

IEEE Spectrum highlights two research paths that try to rethink how high-bandwidth memory is built for AI systems. Instead of simply making taller DRAM stacks, researchers are exploring structures that place memory dies side by side and connect them to processors in new ways. The motivation is clear: AI accelerators need more memory bandwidth and capacity, but taller HBM stacks create thermal and wiring challenges. The article discusses V-Die work from South Korean researchers and MOSAIC work from Japanese researchers, both aimed at improving memory density or bandwidth without letting heat become the limiting factor. For RamTrend, this is a long-term technology signal rather than a pricing event. If such architectures mature, they could reshape future HBM4-and-beyond roadmaps by reducing thermal limits and increasing effective capacity near accelerators. For now, the work remains research-stage and does not change near-term HBM supply.