Qualcomm Maps Out LPDDR-Based Alternative to HBM for Future AI Accelerators

Qualcomm has disclosed HBC Gen 1, a memory-and-compute package that stacks LPDDR dies vertically and links them with through-silicon vias. The design places a compute die at the base to handle near-memory processing, positioning the technology as an alternative to traditional HBM approaches for AI accelerators. According to the company, HBC Gen 1 reached 133 TB/s of bandwidth on its AI250 accelerator and improved bandwidth per watt by roughly six times versus current HBM specifications cited in the announcement. Qualcomm also said this represents an 18x bandwidth gain over the LPDDR5X memory used in its AI200 card, with first deployment targeted for mid-2027 and a second-generation follow-up already on the roadmap. For the memory market, the announcement matters more as a technology signal than as an immediate pricing event. It points to rising interest in stacked low-power memory and advanced packaging for AI systems, but commercial volume and supply effects remain uncertain until product timing, yields, and adoption become clearer.