Intel Foundry outlines packaging path for larger HBM-linked AI systems

At ECTC 2026, Intel Foundry and its collaborators presented packaging research aimed at scaling AI and HPC hardware beyond traditional reticle and substrate limits. The memory-relevant element is EMIB-T, which Intel says can support large multi-die packages with high-bandwidth logic-to-HBM connectivity for accelerator and server designs. The company said its engineers demonstrated first-layer interconnect pitch down to 25 micrometers, package sizes up to 120 by 120 millimeters, and more than nine reticles of compute and memory silicon in one package. Intel also cited signal and power integrity above 12 Gb/s for HBM4e links and 64 Gb/s for UCIe interfaces. Additional work on co-packaged optics, glass substrates, and thermal and bonding methods is intended to ease bandwidth, power, and scaling constraints in future data-center systems. For memory markets, the message is indirect but important: advanced packaging is becoming a gating technology for the next wave of HBM deployment in AI infrastructure. If these approaches mature in production, they could support stronger long-term demand for premium memory attached to increasingly complex accelerator packages.