Monolithic 3D silicon research hints at denser future memory paths

IEEE Spectrum described University of Illinois Urbana-Champaign research into monolithic 3D silicon circuits built by transferring very thin silicon layers onto a wafer at low temperature. The compact payload says the approach avoids some limits of conventional layer stacking and could enable much denser vertical connectivity than through-silicon-via-based 3D integration. The memory-market angle is long range. The article notes potential relevance for advanced computing and memory such as DRAM, and reports that the researchers built circuits across three layers, including SRAM cells with a smaller footprint than a 2D layout. This is not a near-term DRAM or NAND supply event, but it is a useful signal about technology paths that could influence density, yield, and architecture tradeoffs if they become manufacturable at scale.